A hardware-software co-design framework for adaptive, energy-efficient training and pruning of photonic neural networks

Background

Silicon photonic neural networks (PNNs) have emerged as a promising platform for accelerating artificial intelligence (AI) computations due to their inherent advantages of high bandwidth, low latency, and compatibility with established CMOS fabrication processes. Among various photonic architectures, those based on microring resonators (MRRs) are particularly attractive for large-scale integration, leveraging compact footprints and the ability to perform parallel computations using wavelength-division multiplexing. As AI models grow in size and complexity, there is increasing demand for scalable, energy-efficient hardware capable of supporting real-time inference and learning, especially in edge computing and data center applications. Photonic approaches are well-suited to address the limitations of electronic accelerators, such as heat dissipation and bandwidth bottlenecks, but their practical deployment hinges on overcoming unique challenges associated with photonic device variability and control.

Despite their potential, MRR-based PNNs face significant hurdles stemming from fabrication process variations and environmental fluctuations, such as temperature and polarization changes. These factors cause unpredictable shifts in the resonance wavelengths of MRRs, leading to inaccuracies in the mapping of neural network weights and necessitating constant power-hungry tuning to maintain performance. Current approaches typically rely on post-fabrication calibration, static look-up tables, or continuous thermo-optic tuning to compensate for these variations, which not only add complexity but also incur substantial static power consumption. This limits the scalability and energy efficiency of PNNs, making it difficult to deploy large, high-performance photonic neural networks in practical settings. Furthermore, traditional training methods are ill-suited for direct hardware adaptation, as they often require complex gradient calculations and do not account for the dynamic nature of photonic devices, exacerbating the challenges of maintaining accuracy and low power consumption in real-world environments.

Technology

The described technology is an integrated framework for training and optimizing photonic neural network (PNN) chips based on microring resonators (MRRs), specifically designed to address challenges arising from fabrication inconsistencies and environmental fluctuations. The system comprises a PNN chip with arrays of MRRs, optical input/output components, and a central processing unit (CPU) that manages real-time adaptation. Neural network parameters are mapped directly to the MRR tuning currents, allowing the hardware to dynamically adjust to variations. Training is conducted online using a perturbation-based gradient estimation algorithm that relies solely on forward inference, eliminating the need for complex backpropagation. A distinguishing feature is the inclusion of a power-aware pruning term in the loss function, which penalizes high tuning power and enables the selective pruning of less critical MRR weights, thereby optimizing both accuracy and energy efficiency during the training process.

This technology is differentiated by its holistic approach to both adaptivity and energy efficiency in photonic neural networks. Unlike traditional methods that depend on static calibration or post-fabrication corrections, this solution enables real-time, chip-in-the-loop learning that compensates for both static and dynamic variations without additional hardware complexity. The power-aware pruning mechanism is seamlessly integrated into the training loop, allowing the system to significantly reduce tuning power—by up to 83% in large-scale simulations—while maintaining high accuracy. Experimental results on tasks such as Iris classification and RF fingerprinting demonstrate superior performance and robustness compared to conventional offline training. The framework’s scalability, hardware simplicity, and versatility make it a compelling solution for deploying large-scale, energy-efficient photonic AI accelerators in applications ranging from edge computing to LiDAR and RF beamforming.

Benefits

• Real-time adaptation to fabrication variations and environmental fluctuations, maintaining high network accuracy.
• Significant reduction in power consumption through integrated power-aware pruning of microring resonator tuning currents.
• Elimination of complex calibration look-up tables by directly mapping neural network parameters to hardware tuning currents.
• Hardware-efficient gradient estimation using perturbation-based algorithm derived solely from forward inference.
• Scalability to large-scale photonic neural networks and deep convolutional architectures.
• Compatibility with existing silicon photonic integrated circuits and potential extension to other neuromorphic hardware platforms.
• Improved energy efficiency and reduced static power costs enable practical deployment in AI acceleration and photonic applications.
• Maintains performance under temperature variations and dynamic environmental conditions without additional hardware complexity.

Applications

• Edge AI acceleration for smart devices
• Energy-efficient data center inference
• Real-time RF signal classification
• Photonic LiDAR signal processing
• Adaptive optical network switching

Additional info

This system details an online training and pruning method for microring resonator-based photonic neural network chips. It directly maps network parameters to MRR tuning currents, adapting to hardware variations. A perturbation-based gradient estimation, derived from forward inference, updates currents. A power-aware term in the loss function penalizes high tuning power, simultaneously optimizing accuracy and energy efficiency by effectively pruning less critical MRR weights.